The present invention relates to a store control method for a computer system and, more particularly, to a store control method for deciding the priority of access requests in plural states, while assuring the order of the plural access requests to he issued from each access request control circuit in a plurality of access request controllers.
Heretofore, for instance, Japanese Patent Laid-open (Kokai) Publication No. 60-136,849 has disclosed a store control method of a computer system, in which plural access request controllers issue access requests to a storage comprised of plural store banks each store bank being an independently accessible store unit, by adding access request identification data to the access requests. This allows read data to return to the access request controller in the order of issuance of the access requests by continuously issuing access requests in proportion to the kinds of access request identification data without particularly determining if priority is established to the preceding plural access requests, and by judging the access request identification data added to the access requests even if the order of access requests would he changed during processing.
Further, Japanese Patent Laid-open (Kokai) Publication No. 62-251,956 discloses a store control method for performing the synchronous and parallel processing of the access requests from an access request controller that is capable of returning the synchronous and parallel read data to the access request controller, even if disorder of parallel operation would be caused during the processing of access requests, by detecting a previous decision regarding the priority of all access requests having identical access request identification data and by performing store control so as to return to the access request controller.
U.S. Pat. No. 4,745,545 discloses a store control method that solves contention of access requests at multiple stages in a multiprocessor consisting of a main storage having plural "sections", working as store units, and plural processors.
In such conventional store control methods, the access request identification data to be added to each access request enables a following access request to be issued without regard to whether the preceding access requests have been selected by all access request priority determining circuits. By adding the access request identification data to the access request and performing store control by distinguishing individual access requests from each other, the access request can be issued at any arbitrary timing.
Therefore, for example, as shown by the timing chart of FIG. 2, an access request b.sub.0, with access request identification data i.sub.0 added thereto subsequent to issuance of the access request a.sub.0 having the identical access request identification data i.sub.0, can be issued again after the selection of the preceding access request a.sub.0 has been returned as a report signal from all access request priority determining circuits and the report signal has been received. Hence, a sufficient number of kinds of preset access request identification data should be prepared in advance. For instance, the access request identification data are to be prepared in number sufficient to issue a large number of the access requests, without interruption, until the next access request b.sub.0 is issued and a report signal, indicative of the selection of the access request a.sub.0, has been received by all of the access request priority determining circuits. Therefore, in order to effectively accept and process the access request in the store control, a great number of kinds of the access request identification data are required where a number of access request priority determining circuits is provided and set in multiple stages.
In the main storage, however, the access request is stepwise distributed into the target store banks by each of the access request priority determining circuits in accordance with the contents of a main store address. Hence, the store controller which accepts the access request and which performs the store control stores a device number of the access request controller which has issued the access request, reports the result of selection by all of the access request identification data, and transmits the data read from each store bank to the access request controller. Therefore, the store controller must manage the access requests and control data identifying the access requests for processing the store control. However, as the number of kinds of access request identification data becomes larger, the storage and processing required for the control data for the store control increase, thereby reducing the throughput of the store control.
The control data identifying the access request, such as access request identification data and the number for identifying the access request control circuit issuing the access request, do not particularly require all of the control data at each stage of a multiple-stage access request priority determining circuit.